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參數(shù)資料
| 型號(hào)： | KS8808A |
| 廠(chǎng)商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PLL Frequency Synthesizer for Pager(呼機(jī)的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成傳呼機(jī)（呼機(jī)的鎖相環(huán)頻率合成器） |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大小： | 91K |
| 代理商： | KS8808A |
KS8808A
PLL Frequency Synthesizer for Pager
TEL-98-D001-R1
Jan 1998
Preliminary
PIN CONFIGURATION
PIN DESCRIPTION
Pin No
Symbol
Description
1
2
3
OSCI
OSCO
The highest potential supply terminal that can be supplied up to
2.0 V ~ 3.3 V, except for V
DD1.
These input / output pins generate the reference frequency.
In case of OSCI Pin, external reference frequency can be
input through an AC coupling.
I/O
I
O
V
DD2
-
PDA
O
The Output of RX Phase detector terminal for active loop filter.
There are 3 - kinds of output signal states according to Rx Loop Error;
- If Fr > Fn ( Fr is leading ), the output is negative pulse state,
- If Fr < Fn ( Fr is lagging ), the output is positive pulse state,
- If Fr = Fn ( the same phase ), the output is high impedance state.
4
5
The Output of RX Phase detector terminal for passive loop filter .
There are 3 - kinds of output signal states according to Rx Loop Error:
- If Fr
Fn ( Fr is lagging ), the output is negative pulse state,
- If Fr
!
Fn ( Fr is leading ), the output is positive pulse state,
- If Fr = Fn ( the same phase ), the output is high impedance state.
PDP
O
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
KS8808D
OSCI
OSCO
V
DD2
PDA
PDP
V
SS
Fin
V
DD1
NC
Fr
Fn
EN
DATA
CLK
LDT
NC
3
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