參數(shù)資料
型號(hào)： KS8721SL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 6/33頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL EXPERIMENT KS8721SL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8721SL
主要屬性： 1 個(gè)端口，100BASE-TX/100BASE-FX/10BASE-T
次要屬性： MII，RMII，自動(dòng) MDI，MDIX，>130 米線纜驅(qū)動(dòng)器，LDO，符合 IEEE802.3u 要求
已供物品： 板
相關(guān)產(chǎn)品： KS8721SLA4 TR-ND - TXRX 10/100 3.3V 48-SSOP
KS8721SLA4-ND - TXRX 10/100 3.3V 48-SSOP
KS8721SL-ND - TXRX 10/100 3.3V 48-SSOP
KS8721SLI-ND - IC TXRX PHY 10/100 3.3V 48SSOP
KS8721SL TR-ND - IC TXRX PHY 10/100 3.3V 48SSOP
其它名稱： 576-1010
KS8721BL/SL
Micrel
M9999-051704
14
May 2004
to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously
with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted
for transmission by the PHY. TXD[1:0] remains as “00” to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other
than “00” when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than “00” on
TXD[1:0] while TX_EN is de-asserted are ignored by the PHY.
Collision Detection
Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably
regenerates the COL signal of the MII by ANDing TX_EN and CRS_DV.
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a
self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL signal.
Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since
the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.
RX_ER
The PHY provides RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11–
Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a coding error
or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) is detected
somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to
REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC.
RMII AC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
t
SU
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER
4
ns
t
H
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER
2
ns
Data Hold from REF_CLK
Rising Edge
Unused RMII Pins
Input Pins
TXD[2:3] and TXER are pull-down to GND.
Output Pins
RXD[2:3] and RXC are no connect.
Note that the RMII pin needs to be pulled up to enable RMII mode.
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