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參數資料
| 型號： | KS8721SL-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數： | 5/33頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8721SL |
| 標準包裝： | 1 |
| 主要目的： | 接口，以太網控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8721SL |
| 主要屬性： | 1 個端口，100BASE-TX/100BASE-FX/10BASE-T |
| 次要屬性： | MII，RMII，自動 MDI，MDIX，>130 米線纜驅動器，LDO，符合 IEEE802.3u 要求 |
| 已供物品： | 板 |
| 相關產品： | KS8721SLA4 TR-ND - TXRX 10/100 3.3V 48-SSOP KS8721SLA4-ND - TXRX 10/100 3.3V 48-SSOP KS8721SL-ND - TXRX 10/100 3.3V 48-SSOP KS8721SLI-ND - IC TXRX PHY 10/100 3.3V 48SSOP KS8721SL TR-ND - IC TXRX PHY 10/100 3.3V 48SSOP |
| 其它名稱： | 576-1010 |
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May 2004
13
M9999-051704
KS8721BL/SL
Micrel
asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an
end-of-frame (EOF) marker.
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721BL/
SL asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between Ethernet
PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
It is capable of supporting 10Mbps and 100Mbps data rates.
A single clock reference is sourced from the MAC to PHY (or from an external source).
It provides independent 2-bit wide (di-bit) transmit and receive data paths.
It uses TTL signal levels compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Direction
Signal Name
(w/respect to the PHY)
(w/respect to the MAC)
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data
RX_ER
Output
Input (Not Required)
Receive Error
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and
RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as
an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.
Each PHY device must have an input corresponding to this clock but may use a single clock input for multiple PHYs
implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in
10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are detected, the
carrier is detected.
Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV remains
continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to the
first REF_CLK that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes place (see “Definition
of RXD[1:0] Behavior”).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two
bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a predetermined
value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle when CRS_DV is de-
asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be
defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC/repeater. Upon assertion
of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN is
asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented
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相關代理商/技術參數 |
參數描述 |
|---|---|
| KS8721SLI | 功能描述:IC TXRX PHY 10/100 3.3V 48SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:1,140 系列:AU 類型:收發(fā)器 驅動器/接收器數:1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| KS8737 | 制造商:Micrel Inc 功能描述:IC, PHY TRANSCEIVER, 100MBPS, TQFP-64, Data Rate:100Mbps, Ethernet Type:10BASE-T |
| KS8737-EVAL | 功能描述:BOARD EVAL EXPERIMENT FOR KS8737 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| KS8761 | 制造商:KENDIN 功能描述: |
| KS8803 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:10/15 CH PLL |
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