參數(shù)資料
型號: KS8695X
廠商: Micrel Inc
文件頁數(shù): 7/39頁
文件大?。?/td> 0K
描述: IC SWITCH 10/100 5PORT 208PQFP
標(biāo)準(zhǔn)包裝: 24
類型: 網(wǎng)關(guān)
應(yīng)用: 網(wǎng)絡(luò)和通信
安裝類型: 表面貼裝
封裝/外殼: 208-MQFP,208-PQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
配用: KS8695-EVAL-ND - EVAL KIT EXPERIMENTAL KS8695
576-1005-ND - BOARD EVAL EXPERIMENT KS8695X
October 2004
15
M9999-102604
KS8695X
Micrel
Switch Engine
5-port 10/100 Integrated switch with one WAN and four LAN physical layer transceivers
16Kx32 on-chip SRAM for frame buffering
1.4Gbps on-chip memory bandwidth for wire-speed frame switching
10Mbps, 100Mbps modes of operations for both full and half duplex
Supports port-based VLAN
Support DiffServ priority, IEEE 802.1p-based priority or port-based priority
Integrated address look-up engine, supports 1K absolute MAC addresses
Automatic address learning, address aging, and address migration
Broadcast storm protection
Full-duplex IEEE 802.3x flow control
Half-duplex back pressure flow control
Supports IGMP snooping
Spanning Tree Protocol support
Network Interface
Features five MAC units and five PHY units
Supports 10BASE-T and 100BASE-TX on all LAN ports and WAN port. Also supports 100BASE-FX on WAN port
Supports automatic CRC generation and checking
Supports automatic error packet discard
Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps
Supports full-/half-duplex operation on PHY interfaces
Fully compliant with IEEE 802.3 Ethernet standards
IEEE 802.3 full-duplex flow control and half-duplex backpressure collision flow control
Supports MDI/MDI-X auto-crossover
Peripherals
Twenty-eight interrupt sources, including four external interrupt sources
Normal or fast interrupt mode (IRQ, FIQ) supported
Prioritized interrupt handling
Eight programmable general purpose I/O. Pins individually configurable to input, output, or I/O mode for dedicated
signals.
Two programmable 32-bit timers with watchdog timer capability
High-speed UART interface up to 115kbps
Other Features
Integrated PLL to generate CPU and system clocks
JTAG development interface for ICE connection
208-pin PQFP
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