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參數(shù)資料
| 型號(hào)： | KS0724 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD |
| 中文描述： | 65的COM / 132賽格驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 24/66頁(yè) |
| 文件大小： | 899K |
| 代理商： | KS0724 |
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.8 KS0724
20
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip oscillator and its frequency is nearly independent of V
DD
. This oscillator signal is used
in the voltage converter and display timing generation circuit. The oscillator circuit is only enabled when MS = "H"
and CLS = "H". When on-chip oscillator is not used, CLS pin must be "L" condition. In this time, external clock
must be input from CL pin
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation
clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data which is read to the LCD driver
is completely independent of the access to the display data RAM from the microprocessor. The LCD AC signal, M
is generated from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 9.
In a multiple chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11
shows the M, SYNC, CL, and DISP status.
Table 11. Master and Slave Timing Signal Status
Operation mode
Oscillator
M
CL
DISP
ON (internal clock used)
OFF(external clock used)
-
Output
Output
Input
Output
Input
Input
Output
Output
Input
Master
Slave
COM0
V0
V1
V2
V3
V4
V
SS
COM1
V0
V1
V2
V3
V4
V
SS
V0
V1
V2
V3
V4
V
SS
SEGn
64
65
1
2
3
4
5
6
7
8
9
10
11
12
58
59
60
61
62
63
64
65
1
2
3
4
5
6
CL
FR
Figure 9. 2-frame AC Driving Waveform (Duty Ratio = 1/65)
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