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參數(shù)資料
| 型號(hào)： | KS0108B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Dot matrix LCD Driver(點(diǎn)陣LCD的驅(qū)動(dòng)器) |
| 中文描述： | 點(diǎn)陣LCD驅(qū)動(dòng)器（點(diǎn)陣液晶顯示的驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 9/26頁(yè) |
| 文件大?。?/td> | 227K |
| 代理商： | KS0108B |
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KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
PIN NUM
QFP(TQFP)
3(1)
78(76)
73(71), 8(6)
SYMBOL
INPUT/OUTPUT
DESCRIPTION
V
DD
V
SS
V
EE1.2
Power
For internal logic circuit (+5V
10%)
GND (0V)
For LCD driver circuit
V
SS
=0V, V
DD
=+5V
10% , V
DD
-V
EE
=8V~17V
V
EE1
and V
EE2
is connected by the same voltage.
Bias supply voltage terminals to drive the LCD.
74(72), 7(5)
76(74), 5(3)
77(75), 4(2)
75(73), 6(4)
V0L, V0R
V2L, V2R
V3L, V3R
V5L, V5R
Power
V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be connected
by the same voltage.
Chip selection
In order to interface data for input or output,
the terminals have to be CS1B=L, CS2B=L, and CS3=H.
Alternating signal input for LCD driving.
Address control signal to determine the relation between Y address of
display RAM and terminals from which the data is output.
ADC=H
Y0:S1 ~ Y63:S64
ADC=L
Y0:S64 ~ Y63:S1
Synchronous control signal.
Presets the 6-bit Z counter and synchronizes the common signal with the
frame signal when the frame signal becomes high.
Enable signal.
write mode (R/W=L)
data of DB<0:7> is latched at
the falling edge of E.
read mode (R/W=H)
DB<0:7> appears the reading
data while E is at high level.
2 phase clock signal for internal operation.
Used to execute operations for input/output of display
RAM data and others.
Display synchronous signal.
Display data is latched at rising time of the CL signal and increments the
Z-address counter at the CL falling time.
Data or Instruction.
RS=H
DB<0:7> : Display RAM Data
RS=L
DB<0:7> : Instruction Data
Read or Write.
R/W=H
Data appears at DB<0:7> and can be read
by the CPU while E=H, CS1B=L, CS2B=L
and CS3=H.
R/W=L
Display data DB<0:7> can be written at falling of E
when CS1B=L, CS2B=L and CS3=H.
Data bus.
There state I/O common terminal.
92(90)
91(89)
90(88)
2(100)
1(99)
CS1B
CS2B
CS3
M
ADC
Input
Input
Input
100(98)
FRM
Input
99(97)
E
Input
98(96)
97(95)
CLK1
CLK2
Input
96(94)
CL
Input
95(93)
RS
Input
94(92)
R/W
Input
79~86
(77~84)
DB0~DB7
Input/Output
Select Level
V0L(R), V5L(R)
Non-Select Level
V2L(R), V3L(R)
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