參數(shù)資料
型號(hào): KMPC885ZP80
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁(yè)數(shù): 12/92頁(yè)
文件大?。?/td> 1499K
代理商: KMPC885ZP80
MPC885/MPC880 Hardware Specifications, Rev. 3
12
Freescale Semiconductor
Thermal Calculation and Measurement
7
For the following discussions, P
D
= (V
DDL
×
I
DDL
) + PI/O, where PI/O is the power dissipation of the I/O drivers.
NOTE
The V
DDSYN
power dissipation is negligible.
Thermal Calculation and Measurement
7.1 Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, T
J
, in °C can be obtained from the following equation:
T
J
= T
A
+ (R
θ
JA
×
P
D
)
where:
T
A
= ambient temperature oC
R
θ
JA
= package junction-to-ambient thermal resistance (oC/W)
P
D
= power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation
of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor
of two (in the quantity T
J
–T
A
) are possible.
7.2 Estimation with Junction-to-Case Thermal Resistance
Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance:
R
θ
JA
= R
θ
JC
+ R
θ
CA
where:
R
θ
JA
= junction-to-ambient thermal resistance (oC/W)
R
θ
JC
= junction-to-case thermal resistance (oC/W)
R
θ
CA
= case-to-ambient thermal resistance (oC/W)
R
θ
JC
is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the
case-to-ambient thermal resistance, R
θ
CA
. For instance, the user can change the airflow around the device, add a
heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.
4
Input capacitance is periodically sampled.
5
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(3:7), PA(0:11), PA13, PA15, PB(14:31),
PC(4:15), PD(3:15), PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL.
6
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,
OP(0:3) BADDR(28:30)
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