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參數(shù)資料
| 型號(hào)： | KMM965G512 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx64 SGRAM SODIMM(512Kx64 圖形RAM模塊) |
| 中文描述： | 512Kx64 SGRAM個(gè)SODIMM（512Kx64圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 148K |
| 代理商： | KMM965G512 |
SGRAM MODULE
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
KMM965G512BQ(P)N / KMM966G512BQ(P)N
ELECTRONICS
- 8 -
Rev. 2.5 (July. 1998)
Parameter
Value
AC input levels
V
ih
/V
il
= 2.4V / 0.4V
Input timing measurement reference level
1.4V
Input rise and fall time(See note 3)
t
R
/
t
F
=1ns/ 1ns
Output timing measurement reference level
1.4V
Output load condition
See Fig. 2
3.3V
1200
870
Output
30pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
V
tt
= 1.4V
50
Output
30pF
Z0=50
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
* All AC parameters are measured from half to half.
Parameter
Symbol
-7
-8
-10
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
7
1000
8
1000
10
1000
ns
1
CAS Latency=2
12
12
13
CLK to valid
output delay
CAS Latency=3
t
SAC
-
6
-
6.5
-
7
ns
1, 2
CAS Latency=2
-
8
-
8
-
9
Output data hold time
t
OH
2.5
2.5
2.5
ns
2
CLK high pulse width
t
CH
2.5
3
3.5
ns
3
CLK low pulse width
t
CL
2.5
3
3.5
ns
3
Input setup time
t
SS
2
2.5
2.5
ns
3
Input hold time
t
SH
1
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
-
6
-
6.5
-
7
ns
CAS latency=2
-
8
-
8
-
9
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