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參數(shù)資料
| 型號(hào)： | KMM466F404BS2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 64 DRAM SODIMM(4M x 64 動(dòng)態(tài) RAM模塊) |
| 中文描述： | 4米× 64內(nèi)存的SODIMM（4米× 64動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 403K |
| 代理商： | KMM466F404BS2 |
DRAM MODULE
KMM466F404BS2-L
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Symbol
-5
-6
Unit
Note
Min
45
47
5
10
5
Max
Min
53
58
5
10
5
Max
Column address to W delay time
CAS precharge to W delay time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper page mode cycle time
Hyper page mode read-modify write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width(Hyper page cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
HPRWC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
OEA
t
OED
t
OEZ
t
OEH
t
DOH
t
REZ
t
WEZ
t
WED
t
OCH
t
CHO
t
OEP
t
WPE
t
RASS
t
RPS
t
CHS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
6
6
16
17
28
35
3
10
10
13
20
67
7
50
30
10
10
25
73
10
60
35
10
10
200K
200K
13
15
3
10
3
5
5
3
3
15
5
5
5
5
100
90
-50
13
3
5
5
3
3
15
5
5
5
5
100
110
-50
13
13
13
13
15
15
11
19,20,21
19,20,21
19,20,21
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C, V
CC
=3.3V
±
0.3V. See notes 1,2.)
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