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參數資料
| 型號： | KMM378S3320T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Mx72 SDRAM DIMM(32M x 72 動態(tài) RAM模塊) |
| 中文描述： | 32Mx72 SDRAM的內存（32M × 72配置動態(tài)內存模塊） |
| 文件頁數： | 4/11頁 |
| 文件大小： | 182K |
| 代理商： | KMM378S3320T |
SDRAM MODULE
KMM378S3320T
REV. 0 Mar. '98
Preliminary
*1. Register Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
RAS
CAS
WE
RAS
CAS
WE
CAS latency(refer to *1)
=2CLK+1CLK
tSAC
tRDL
Read
Command
Row Active
Precharge
Command
Row Active
Write
Command
Precharge
Command
1CLK
td
tr
td
tr
td, tr = Delay of Register (SN74ALVCH162836 of TI)
Note :
1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (SN74ALVCH162836). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D
IN
is to be issued 1clock after write command in external timing because D
IN
is issued directly to module.
: Don
′
t
Care
STANDARD TIMING DIAGRAM WITH PLL & REGISTER(CL=2,BL=4)
*2. Register Output
*3. SDRAM
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3
D
OUT
tRAC(refer to *1)
tRAC(refer to *2)
CAS latency(refer to *2)
=2CLK
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
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