參數(shù)資料
型號(hào)： KMM378S1723T
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 16Mx72 SDRAM DIMM(16M x 72 動(dòng)態(tài) RAM模塊)
中文描述： 16Mx72 SDRAM的內(nèi)存（1,600 × 72動(dòng)態(tài)內(nèi)存模塊）
文件頁數(shù)： 1/11頁
文件大?。?/td> 159K
代理商： KMM378S1723T
SDRAM MODULE
KMM378S1723T
REV. 1 April. '98
Preliminary
The Samsung KMM378S1723T is a 16M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
KMM378S1723T consists of nine CMOS 16M x 8 bit Synchro-
nous DRAMs in TSOP-II 400mil packages, two 20 bits Drive ICs
for input control signal and one PLL in 24-pin TSOP package
mounted on a 200-pin glass-epoxy substrate. Two 0.1uF deco-
pling capacitors are mounted on the printed circuit board for
each SDRAM. The KMM378S1723T is a Dual In-line Memory
Module and is intended for mounting into 200-pin edge connec-
tor sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high band-
width, high performance memory system applications.
Performance range
Part No. Max Freq. (Speed)
KMM378S1723T-G8 125MHz (8ns @ CL=3)
KMM378S1723T-GH 100MHz (10ns @ CL=2)
KMM378S1723T-GL 100MHz (10ns @ CL=3)
KMM378S1723T-G0 100MHz (10ns @ CL=3)
Burst Mode Operation
Auto & Self Refresh Capability (4096 cycles / 64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
PCB :
Height(1,250mil)
, double sided component
FEATURE
GENERAL DESCRIPTION
KMM378S1723T
16Mx72 SDRAM DIMM with PLL & Register based on 16Mx8, 4Banks, 4K Ref. 3.3V Synch. DRAMs
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
PIN CONFIGURATIONS (Front Side / Back Side)
Note
:1. "*" ; These pins are not used in this synchronous DRAM module. Here these pins are equal to No Connection.
2. In LVTTL interface, V
DDQ
=V
DD and VSSQ=VSS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Front
V
DD
NC
NC
*IN
*OUT
NC
NC
V
SS
DQ67
DQ66
V
DDQ
DQ65
DQ64
V
SS
DQ63
DQ62
NC
DQ61
DQ60
V
DDQ
NC
NC
V
SS
NC
NC
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Front
V
DDQ
DQ51
DQ50
V
SS
DQ49
DQ48
V
DDQ
DQ43
DQ42
V
SS
DQ41
DQ40
V
DDQ
A4
A5
V
SS
A8
A9
V
DD
NC
CKE0
V
SS
CAS
NC
V
DD
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Front
V
SS
RAS
V
SS
*A12/CS2
A11
V
DD
A0
A1
V
SS
DQ35
DQ34
V
DDQ
DQ33
DQ32
V
SS
DQ27
DQ26
V
DDQ
DQ25
DQ24
V
SS
DQ19
DQ18
V
DDQ
DQ17
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Front
DQ16
V
SS
NC
NC
V
DDQ
DQ15
DQ14
V
SS
DQ13
DQ12
V
DDQ
DQ7
DQ6
V
SS
DQ5
DQ4
V
DDQ
NC
NC
NC
NC
NC
SCL
NC
V
SS
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
Back
NC
NC
V
SS
REGE
RFU
RFU
NC
DQ71
DQ70
V
SS
DQ69
DQ68
V
DDQ
NC
V
SS
NC
DQ59
DQ58
V
SS
DQ57
DQ56
V
DDQ
DQ55
DQ54
V
SS
Pin
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
DQ53
DQ52
V
DDQ
DQ47
DQ46
V
SS
DQ45
DQ44
V
DDQ
DQ39
DQ38
V
SS
DQ37
DQ36
V
DD
A6
A7
V
SS
BA0(A13)
NC
V
DD
DQM
WE
V
SS
NC
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Back
CLK0
V
DD
NC
CS0
V
SS
BA1
A10(AP)
V
DD
A2
A3
V
SS
DQ31
DQ30
V
DDQ
DQ29
DQ28
V
SS
DQ23
DQ22
V
DDQ
DQ21
DQ20
V
SS
NC
NC
Pin
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Back
V
DD(Q)
NC
V
SS
V
SS
NC
NC
V
DDQ
DQ11
DQ10
V
SS
DQ9
DQ8
V
DDQ
DQ3
DQ2
V
SS
DQ1
DQ0
SDA
SA0
SA1
SA2
V
DD
NC
NC
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