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參數(shù)資料
| 型號(hào)： | KMM366S1723TL |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16Mx64 SDRAM DIMM(16Mx64 動(dòng)態(tài) RAM模塊) |
| 中文描述： | 16Mx64 SDRAM的內(nèi)存（16Mx64動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | KMM366S1723TL |
PC66 SDRAM MODULE
KMM366S1723TL
REV. 0 Mar. '98
Preliminary
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
′
t Care, H=Logic High, L=Logic Low)
Note :
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
11,
A
9
~ A
0
Note
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1, 2
Refresh
Auto Refresh
H
H
L
L
L
H
X
X
3
Self
Refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Read &
Column Address
Auto Precharge Dis-
H
X
L
H
L
H
X
V
L
Column
Address
(A
0
~A
9
)
4
Auto Precharge Enable
H
4, 5
Write &
Column Address
Auto Precharge Dis-
H
X
L
H
L
L
X
V
L
Column
Address
(A
0
~A
9
)
4
Auto Precharge Enable
H
Burst Stop
H
X
L
H
H
L
X
X
6
Precharge
Bank Selection
H
X
L
L
H
L
X
V
L
X
All Banks
X
H
Clock Suspend or
Active Power Down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge Power Down
Mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
V
X
7
No Operation Command
H
X
H
X
X
X
X
X
L
H
H
H
1. OP Code : Operand Code
A
0
~ A
11
& BA
0
~ BA
1
: Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If both BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank B is selected.
If both BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
X
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