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參數(shù)資料
| 型號： | KM736V787 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36-Bit Synchronous Burst SRAM(128Kx36位同步靜態(tài) RAM) |
| 中文描述： | 128K × 36至位同步突發(fā)靜態(tài)存儲器（128K × 36至位同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 344K |
| 代理商： | KM736V787 |
KM736V787
128Kx36 Synchronous SRAM
- 6 -
Rev 1.0
May. 1998
OPERATING CONDITIONS
(0
°
C
≤
TA
≤
70
°
C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
V
DD
3.135
3.3
3.6
V
V
DDQ
3.135
3.3
3.6
V
Ground
V
SS
0
0
0
V
CAPACITANCE*
(T
A
=25
°
C, f=1MHz)
*NOTE
: Sampled not 100% tested.
Parameter
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
=0V
-
5
pF
Output Capacitance
C
OUT
V
OUT
=0V
-
8
pF
TEST CONDITIONS
(T
A
=0 to 70
°
C, V
DD
=3.3V+0.3V/-0.165V, unless otherwise specified)
Parameter
Value
Input Pulse Level
0 to 3V
Input Rise and Fall Time(Measured at 0.3V and 2.7V)
2ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Fig. 1
DC ELECTRICAL CHARACTERISTICS
(T
A
=0 to 70
°
C, V
DD
=3.3V+0.3V/-0.165V)
* V
IL
(Min)=-2.0(Pulse Width
≤
t
CYC
/
2)
** V
IH
(Max)=4.6(Pulse Width
≤
t
CYC
/
2)
** In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.5V
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current(except ZZ)
I
IL
V
DD
=Max , V
IN
=V
SS
to V
DD
-2
+2
μ
A
μ
A
Output Leakage Current
I
OL
Output Disabled, V
OUT
=V
SS
to V
DDQ
-2
+2
Operating Current
I
CC
Device Selected, I
OUT
=0mA,
ZZ
≤
V
IL
, All Inputs=V
IL
or V
IH
Cycle Time
≥
t
CYC
min
-7
-
350
mA
-8
-
325
-9
-
300
Standby Current
I
SB
Device deselected,
I
OUT
=0mA, ZZ
≤
V
IL
, f=Max,
All Inputs
≤
0.2V or
≥
V
DD
-0.2V
-7
-
100
mA
-8
-
90
-9
-
80
I
SB1
Device deselected, I
OUT
=0mA,
ZZ
≤
0.2V, f=0,
All Inputs=fixed (V
DD
-0.2V or 0.2V)
-
30
mA
I
SB2
Device deselected, I
OUT
=0mA,
ZZ
≥
V
DD
-0.2V, f=Max,
All Inputs
≤
V
IL
or
≥
V
IH
-
30
mA
Output Low Voltage
V
OL
I
OL
=8.0mA
-
0.4
V
Output High Voltage
V
OH
I
OH
=-4.0mA
2.4
-
V
Input Low Voltage
V
IL
-0.5*
0.8
V
Input High Voltage
V
IH
2.0
V
DD
+0.5**
V
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