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參數(shù)資料
| 型號： | KM736V695 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx36-Bit Synchronous Pipelined Burst SRAM(64Kx36位同步流水線脈沖 靜態(tài) RAM) |
| 中文描述： | 64Kx36位同步流水線突發(fā)靜態(tài)存儲器（64Kx36位同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 314K |
| 代理商： | KM736V695 |
PRELIMINARY
KM736V695/L
64Kx36 Synchronous SRAM
- 2 -
Rev 1.1
April 1997
WEc
WEd
OE
64Kx36-Bit Synchronous Pipelined Burst SRAM
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
Core Supply Voltage : 3.3V
±
5%
I/O Supply Voltage : 2.5V+0.4/-0.13V.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a
linear burst.
Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A
The KM736V695/L is a 2,359,296-bit Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 65,536 words of 36bits and integrates
address and control registers, a 2-bit burst address counter and
added some new functions for high performance cache RAM
applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP disable to support address pipelining.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM736V695/L is fabricated using SAMSUNG
′
s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
GENERAL DESCRIPTION
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
ZZ
DQa
0
~ DQd
7
DQPa ~ DQPd
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
64Kx36
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTERS
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0
~
A
′
1
A
0
~
A
1
A
2
~
A
15
A
0
~
A
15
FAST ACCESS TIMES
Parameter
Symbol
- 7
-8
-10
Unit
Cycle Time
t
CYC
7.5
8.6
10
ns
Clock Access Time
t
CD
5.0
5.0
5.5
ns
Output Enable Access Time
t
OE
4.8
5.0
5.5
ns
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