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參數(shù)資料
| 型號： | KM718V949 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx18-Bit No Turnaround SRAM(512Kx18位數(shù)據(jù)流無返回靜態(tài) RAM) |
| 中文描述： | 512Kx18位無轉(zhuǎn)機(jī)的SRAM（512Kx18位數(shù)據(jù)流無返回靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 276K |
| 代理商： | KM718V949 |
PRELIMINARY
KM736V849
KM718V949
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 10 -
Rev 0.1
Aug. 1998
AC TIMING CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0 to 70
°
C)
NOTE
: 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature t
CLZ
is more than t
HZC.
The specs as shown do not imply bus contention because t
CLZ
is a Min. parameter that is worst case at totally different test conditions
(0
°
C,3.465V) than t
CHZ
, which is a Max. parameter(worst case at 70
°
C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. ADV must not be asserted for at least 2 Clocks after leaving ZZ state.
Parameter
Symbol
-67
-75
-10
Unit
Min
Max
Min
Max
Min
Max
Cycle Time
t
CYC
6.7
-
7.5
-
10.0
-
ns
Clock Access Time
t
CD
-
3.8
-
4.0
-
5.0
ns
Output Enable to Data Valid
t
OE
-
3.8
-
4.0
-
5.0
ns
Clock High to Output Low-Z
t
LZC
1.5
-
1.5
-
1.5
-
ns
Output Hold from Clock High
t
OH
1.5
-
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
t
LZOE
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
-
3.0
-
3.5
-
3.5
ns
Clock High to Output High-Z
t
HZC
-
3.0
-
3.5
-
3.5
ns
Clock High Pulse Width
t
CH
2.5
-
3.0
-
3.0
-
ns
Clock Low Pulse Width
t
CL
2.5
-
3.0
-
3.0
-
ns
Address Setup to Clock High
t
AS
1.5
-
1.5
-
1.5
-
ns
CKE Setup to Clock High
t
CES
1.5
-
1.5
-
1.5
-
ns
Data Setup to Clock High
t
DS
1.5
-
1.5
-
1.5
-
ns
Write Setup to Clock High (WE, BW
X
)
t
WS
1.5
-
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
t
ADVS
1.5
-
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
t
CSS
1.5
-
1.5
-
1.5
-
ns
Address Hold from Clock High
t
AH
0.5
-
0.5
-
0.5
-
ns
CKE Hold from Clock High
t
CEH
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
t
DH
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High (WE, BWE
X
)
t
WH
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
t
ADVH
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
t
CSH
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
t
PDS
2
-
2
-
2
-
cycle
ZZ Low to Power Up
t
PUS
2
-
2
-
2
-
cycle
Output Load(B),
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
353
/
1538
5pF*
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
/
1667
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50
RL=50
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
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