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參數(shù)資料
| 型號： | KM718V895 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx18 Synchronous SRAM(256Kx18位同步靜態(tài) RAM) |
| 中文描述： | 256Kx18同步SRAM（256Kx18位同步靜態(tài)內存） |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 314K |
| 代理商： | KM718V895 |
KM718V895
256Kx18 Synchronous SRAM
- 2 -
Rev 1.0
May 1998
WEa
WEb
256Kx18-Bit Synchronous Pipelined Burst SRAM
The KM718V895 is a 4,718,592 bits Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of pentium and Power PC based system.
It is organized as 256K words of 18 bits. And it integrates
address and control registers, a 2-bit burst address counter and
added some new functions for high performance cache RAM
applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP disable to support address pipelin-
ing.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence (linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM718V895 is fabricated using SAMSUNG
′
s high perfor-
mance CMOS technology and is available in a 100pin TQFP.
Multiple power and ground pins are utilized to minimize ground
bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
2 Stage Pipelined Operation With 4 Burst
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
=3.3V+0.3V/-0.165V Power Supply.
I/O Supply Voltage 2.5V+0.4V/-0.13V.
5V Tolerant Inputs except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
Three Chip Enables for simple depth expansion with No Data
Contention ; 2 cycle Enable, 1 cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
OE
ZZ
DQa
~ DQb
7
DQPa ~ DQPb
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
256Kx18
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0
~
A
′
1
A
0
~
A
1
A
2
~
A
17
A
0
~
A
17
FAST ACCESS TIMES
Parameter
Symbol 60
67
72
85 Unit
Cycle Time
t
CYC
6.0 6.7 7.2 8.5
ns
Clock Access Time
t
CD
3.5 3.8 4.0 4.0
ns
Output Enable Access Time
t
OE
3.5 3.8 4.0 4.0
ns
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