參數(shù)資料
型號： KM416V254DL
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256K x 16Bit CMOS Dynamic RAM with Extended Data Out(256K x 16位 CMOS 動態(tài)RAM（帶擴展數(shù)據(jù)輸出）)
中文描述： 256 × 16位分辨率的CMOS擴展數(shù)據(jù)輸出動態(tài)存儲器（256K × 16位的CMOS動態(tài)隨機存儲器（帶擴展數(shù)據(jù)輸出））
文件頁數(shù)： 7/36頁
文件大小： 777K
代理商： KM416V254DL
KM416C254D/DL, KM416V254D/DL
CMOS DRAM
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 50pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycles is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in ealy write cycles and to the W falling edge in OE controlled
write cycle and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
t
ASC
≥
6ns, Assume tT = 2.0ns
512cycle of burst refresh must be executed within 8ms before and after self refresh in order to meet refresh specification (L-
version).
KM416C/V254D/DL Truth Table
RAS
H
LCAS
H
UCAS
H
W
H
OE
H
DQ0 - DQ7
Hi-Z
DQ8-DQ15
Hi-Z
STATE
Standby
L
H
H
H
H
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
7.
6.
5.
10.
9.
8.
12.
11.
3.
2.
1.
4.
NOTES
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