參數(shù)資料
型號(hào)： KITMPR083EVM
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/35頁(yè)
文件大小： 0K
描述： KIT EVAL 8POSITION ROTARY TOUCH
標(biāo)準(zhǔn)包裝： 1
傳感器類型： 觸摸，電容式
傳感范圍： 8 個(gè)按鈕/鍵
接口： I²C
電源電壓： 1.8 V ~ 3.6 V
嵌入式： 是，其它
已供物品： 板，纜線，CD
已用 IC / 零件： MPR083
相關(guān)產(chǎn)品： MPR083EJR2CT-ND - IC CTLR TOUCH SENSR PROX 16TSSOP
MPR083QR2-ND - IC CTLR TOUCH SENSOR PROX 16-QFN
MPR083Q-ND - IC CTLR TOUCH SENSOR PROX 16-QFN
MPR083EJR2TR-ND - IC CTLR TOUCH SENSR PROX 16TSSOP
MPR083EJ-ND - IC CTLR TOUCH SENSR PROX 16TSSOP
MPR083
Sensors
Freescale Semiconductor
19
7
Interrupts
7.1
Introduction
The MPR083 has one interrupt output that is configured by registers and alerts the application when a touch or fault is detected.
When running in Run2 or Stop2 mode where I2C communication is not available this feature alerts the user to sensor touches.
7.2
Condition for Interrupt
There are two cases that latch the Interrupt buffered data available or fault detected.
7.2.1
Buffered Data Available
The interrupt for Buffered Data Available will only trigger when the NDF (No Data Flag) transitions from high to low. This signifies
that there is new data available in the buffer. The interrupt is deasserted on the first read/write of the FIFO Register and cannot
be reasserted for buffered data until the FIFO is empty (either by reading all the data, or clearing the buffer).
7.2.2
Fault Detected
The interrupt for a fault detected condition is triggered any time the Fault condition in the Fault Register transitions from zero to
non-zero. The interrupt is deasserted when the Fault Register is cleared (by writing to the Fault Register).
7.3
Settings
Interrupts are configured through I2C using the Configuration Register (Section 4.7). Two of the settings in this register will affect
the interrupt functionality.
The Interrupt Enable (IRQEN) must be set high for the IRQ to be enabled. When low, all interrupts will be ignored, and the IRQ
pin will never latch.
The Interrupt Rate (IRQR) sets the minimum delay between sequential triggered interrupts. The minimum interrupt period can be
calculated by taking the product of the (MTP + 5) and IRQR with a factor of 4. Thus, for the minimum setting an interrupt would
be triggered no more often than 4 times the master clock.
Equation 4
If the MPR083 is using Run2, the minimum interrupt period would be represented by the following equation.
Equation 5
7.4
IRQ Pin
The IRQ pin is an open-drain, latching interrupt output which requires an external pull-up resistor. The pin will latch down based
on the conditions in Section 6.2. The pin will reset when an I2C transmission reads/writes the appropriate register displaying
information about the source of the interrupt. Thus if the source is buffered data available then a FIFO Buffer read/write will clear
the IRQ pin. If the source is a fault detected then a write of the Fault Register will clear the pin.
MinInterruptPeriod ms
MTP
5
+
IRQR
4
=
MinInterruptPeriod ms
MTP
5
+
8
----------------------
1
+
8
I
RQR 4
=
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