
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
7
Device Architecture
   
Design Technology:           
   
Supply Voltage:                                  
   
Host Interface:                                     
   
5KB Internal BufferRAM:                    
   
SLC NAND Array:                                
Device Performance
   
Host Interface Type:
                                                                                                   - Up to 54MHz clock frequency
                                                                                                   - Linear Burst 4-, 8-, 16, 32-words with wrap around
                                                                                                   - Continuous 1K word Sequential Burst
Asynchronous Random Read
           - 76ns access time
Asynchronous Random Write
Latency 3(up to 40MHz), 4, 5, 6, and 7
Up to 4 sectors using Sector Count Register
Cold/Warm/Hot/NAND Flash Resets
up to 64 Blocks
Typical Power,
   
Programmable Burst Read Latency
   
Multiple Sector Read:
   
Multiple Reset Modes:
   
Multi Block Erase
   
Low Power Dissipation:
                                                                                                   - Standby current : 10uA
                                                                                                   - Synchronous Burst Read current(54MHz) : 12mA
                                                                                                   - Load current : 30mA
                                                                                                   - Program current : 25mA
                                                                                                   - Erase current : 20mA
                                                                                                   - Multi Block Erase current : 20mA
           
Reliable CMOS Floating-Gate Technology        - Endurance : 100K Program/Erase Cycles
                                                                                        - Data Retention : 10 Years
System Hardware
   
Voltage detector generating internal reset signal from Vcc
   
Hardware reset input (/RP)
   
Data Protection Modes
   
User-controlled One Time Programmable(OTP) area
   
Internal 2bit EDC / 1bit ECC
   
Internal Bootloader supports Booting Solution in system
   
Handshaking Feature
   
Detailed chip information 
Packaging
   
1G products
   
2G DDP products
90nm
1.8V (1.7V ~ 1.95V)
16 bit 
1KB BootRAM, 4KB DataRAM
(2K+64)B Page Size, (128K+4K)B Block Size
Synchronous Burst Read
- Write Protection for BootRAM 
- Write Protection for NAND Flash Array
- Write Protection during power-up
- Write Protection during power-down
- INT pin indicates Ready / Busy
- Polling the interrupt register status bit 
- by ID register
63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA 
63ball, 11mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA (TBD)
1.5        Product Features