
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
6.14      Toggle Bit Timing  in Asynchronous Read
             (VA Transition Before AVD Low) 
FLASH MEMORY
115
6.15      Toggle Bit Timing in Asynchronous Read 
             (VA Transition After AVD Low) 
                              See AC Characteristics Table 5.5
t
OE
Status RD
1)
t
CE
t
OEZ
t
AVDP
t
AA
CE
OE
WE
A/DQ0:
A/DQ15
AVD
Hi-Z
RDY
2)
t
RC
t
CA
t
CEZ
t
CER
t
AVDO
Hi-Z
t
OE
Status RD
1)
t
OEZ
t
ACC
t
AAVDH
t
AVDP
t
AAVDS
CE
OE
WE
A/DQ0:
A/DQ15
AVD
t
CEZ
t
CA
t
CER
t
AVDO
Hi-Z
Hi-Z
RDY
2)
t
RC
t
CE
Hi-Z
NOTE:
1. VA=Valid Read Address, RD=Read Data.
2. Before IOBE is set to 1, RDY and INT pin are High-Z state. 
3. Refer to chapter 5.5 for tASO description and value.
VA
Status RD
Hi-Z
t
ASO
VA
Status RD
t
CA
t
ASO
t
AAVDH
t
AAVDS
VA
1)
VA
1)
NOTE:
1. VA=Valid Read Address, RD=Read Data.
2. Before IOBE is set to 1, RDY and INT pin are High-Z state. 
3. Refer to chapter 5.5 for tASO description and value. 
                              See AC Characteristics Table 5.5