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參數資料
| 型號： | KFM1216Q2M-DED |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY |
| 中文描述： | 閃存 |
| 文件頁數： | 8/88頁 |
| 文件大?。?/td> | 1150K |
| 代理商： | KFM1216Q2M-DED |
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MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
8
1. FEATURES
Design Technology: 0.12
μ
m
Voltage Supply
- 1.8V device(KFM1216Q2M) : 1.7V~1.95V
Organization
- Host Interface:16bit
Internal BufferRAM(5K Bytes)
- 1KB for BootRAM, 4KB for DataRAM
NAND Array
- Page Size : (2K+64)bytes
- Block Size : (128K+4K)bytes
Architecture
Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz(1.8V device)
: Linear Burst - 4 , 8 , 16 words with wrap-around
: Continuous Sequential Burst(1K words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
Programmable Read latency
Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 4 sectors)
Reset Mode
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
Power dissipation (typical values)
- Standby current : 10uA
- Asynchronous Read current : 8mA
- Synchronous Burst Read current(54MHz) : 12mA
- Load current : 20mA
- Program current: 20mA
- Erase current: 15mA
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Performance
Voltage detector generating internal reset signal from Vcc
Hardware reset input (RP)
Data Protection
- Write Protection mode for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
User-controlled One Time Programmable(OTP) area
Internal 2bit EDC / 1bit ECC
Internal Bootloader supports Booting Solution in system
Hardware Features
Handshaking Feature
- INT pin: Indicates Ready / Busy of MuxOneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of MuxOneNAND
Detailed chip information by ID register
Software Features
Package
- 48ball, 12mm x 9.5mm x max 1.0mmt , 0.5mm ball pitch FBGA
Packaging
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