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參數(shù)資料
| 型號： | KESRX05KG1T |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 260 to 470MHz ASK Receiver with Power Down |
| 中文描述： | 260至470MHz ASK接收機(jī)的斷電 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 466K |
| 代理商： | KESRX05KG1T |
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13
KESRX05
Improving Anti-Jamming Performance
G
Interference rejection (dB) = Interferer (dBm)
2
Wanted
(dBm). The interference rejection of the receiver for
different modulation schemes can be improved by:
G
Changing the value of C2. Increasing the value of C2
may result in pulse stretching of the recovered signal.
G
Adjusting the comparator reference level (DSN) by
offsetting the internal reference (Figure 6) by a high
value resistor from the DSN pin to V
EE
and or the peak
detector output. (Figures 25 and 26).
G
Reducing the bandwidth of the data fillter, intermediate
frequency filter CF1 and/or the noise reduction filter
(L5 C7). Thebandwidth of the receiver must
accommodate tolerancing of the data, transmitter and
receiver.
G
Increasing the value of AGC capacitor C8 to maintain
the level of the AGC controi during the off period of the
wanted modulation signal. This will improve the
interference rejection of the receiver but increase the
time to good data from power-up PD0 to PD2. The
application circuit Figure 26 has been optimised for
time to good data.
G
Changing the value of C10 to allow the anti-jam circuit
to detect/recover alternative data modulation schemes
such as PWM.
Baseband
The RSSI output will contain wide band demodulated noise
and signals which are within the RF and IF filter pass bands.
An additional low pass data filter is therefore used to
improve overall sensitivity.
KESRX05 has an integrated second-order Sallen and Key
data filter whose characteristic is set by R10, R11, C5 and
C6. Figure 10 showsthe connections and calculation for
the
2
3dB cut-off frequency and filter type. The cut-off
frequency is determined from the data rate and the level
of pulse distortion which can be tolerated. The data filter
cut off frequency is usually set at 3 to 5 times the minimum
pulse width period, i.e:
1
Data pulse width
f
C
= 5
3
The output from this filter, DF2, is directly coupled into the
inverting input of the data comparator with a fixed slice
level applied to the non-inverting input, DSN. A peak
detector recovers the signal amplitude on the capacitor.
Normally, the comparator reference level used is the
internal reference, a capacitor at Pin DSN serving to
remove noise pick-up. In order to fine tune the slice level
for sensitivity, squelch and optimum interference rejection
the slice level can be offset from the internal reference by
a high value resistor from the DSN pin to Vee and/or the
peak detector output (Figures 25 and 26).
The data comparator (slicer) output, DATAOP, is CMOS
compatible but is only capable of driving small capacitive
loads,
,
20pF, depending on data rate. With the anti-jam
circuit connected, data output has the inverted sense of
the input signal at DF2.
To invert the sense of the data output with the anti-jam
circuit connected, the buffer transistor circuit shown in
Figure 4 can be used.
NOTE
Buffered DATAOP will squelch low if the input data signal
remains continuously in a high or low state. The time taken
for the buffered data output to squelch low is governed by
the time constant C
IN
R
IN
.
The output drive current is nominally
6
50
μ
A so that a
system using high data rates or higher capacitive loads,
e.g. Iong track lengths, may need to incorporate a buffer
transistor to provide the necessary edge speeds to the
following logic circuits.The comparator has 20mV
hysteresis built-in to reduce edge chatter.
The sense of the squelch on the data output is low when
no signal is present. This may be confusing, as a low output
during the data burst also corresponds to the on period,
i.e. the MARK, of the RF OOK signal. However, it is the
very first pulse of the data signal which causes the DC
restoration capacitor of the anti-jamming circuit to charge
to the correct level appropriate to the final slice level. As a
consequence of this the very first pulse of the data
transmission may be lost as the receiver adapts to the
incoming signal level.
FROM
DATAOP
C
IN
R
IN
R
BIAS
R
OUT
BUFFERED
DATAOP
V
CC
V
EE
High
Low
Buffered state
Low
High
Data state
Data
Data
V
EE
V
CC
Table 4
Figure 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KESRX05QP1S | 260 to 470MHz ASK Receiver with Power Down |
| KESRX05QP1T | 260 to 470MHz ASK Receiver with Power Down |
| KESTX0 | 400MHz - 460MHz ASK Transmitter |
| KESTX01IG | 400MHz - 460MHz ASK Transmitter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KESRX05QP1S | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:260 to 470MHz ASK Receiver with Power Down |
| KESRX05QP1T | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:260 to 470MHz ASK Receiver with Power Down |
| KEST-471BT | 制造商:KEPONT 制造商全稱:KEPONT 功能描述:Sleeve or Ball Bearing |
| KEST-471BW | 制造商:KEPONT 制造商全稱:KEPONT 功能描述:Sleeve or Ball Bearing |
| KEST-471SW | 制造商:KEPONT 制造商全稱:KEPONT 功能描述:Sleeve or Ball Bearing |
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