參數(shù)資料
型號: KESRX05KG1T
廠商: Zarlink Semiconductor Inc.
英文描述: 260 to 470MHz ASK Receiver with Power Down
中文描述: 260至470MHz ASK接收機的斷電
文件頁數(shù): 11/28頁
文件大?。?/td> 466K
代理商: KESRX05KG1T
10
KESRX05
choice of bandwidth for the 10·7MHz ceramic filter depends
on frequency tolerancing of the transmitter, receiver, data
rate and component cost.
The IF filter drive, IFOUT, is a voltage drive with a 300
series resistance (see Table 1, pin 6). This allows
impedance matching to the ceramic IF filter to be set by
an external series resistor. A 10·7MHz ceramic filter with,
typically, a 300
input impedance does not require an
external matching resistor at IFOUT.
The input to the log amp, IFIN, is high impedance with an
internal 3k
shunt resistor. Impedance matching to the
output of the ceramic filter is achieved by an external shunt
resistor R9 between IFIN and IFDC1 (see Table 1, pin 3).
Phase Lock Loop VCO
The local oscillator (LO) is a VCO locked to a crystal
reference by a phase lock loop (PLL). The VCO gain is
nominally 26MHz/V depending on the external varactor
used. The LO frequency is divided by 64 and fed into the
phase-frequency detector, where the reference frequency
is provided from the crystal oscillator. The AC phase
detector output current into the PLL loop filter is nominally
6
15
μ
A. The maximum loop filter bandwidth is 50kHz.
VCO Circuit Design and Layout
The Local Oscillator (LO) frequency is controlled by a
parallel resonant tuned circuit. The frequency of the local
oscillator is controlled by a Phase Locked Loop (PLL),
referenced to the crystal frequency.
Designing for VCO Track Parasitics
To remove the effect of track parasitics the following pro-
cedure should be adopted.
1. Open circuit the control feed back from the PLL con-
trol loop by removing R1.
2. Connect an external Power Supply Unit (PSU = V
CC
/ 2)
in place of R1, LF output (Figure 3).
3. Using a spectrum analyser, monitor the LO level at
the RFIN port. Alternatively use a small pick-up coil to
loosely couple to the signal generated across L2.
4. Note that the LO level is
,,2
65 dBm, range = 300 to
500MHz.
5. Vary the value of the PSU input to confirm that there is
a corresponding change in LO frequency. Set the PSU
at V
CC
/2. If the VCO does not oscillate at V
CC
/2, char-
acterise the LO at an alternative voltage.
6. Using a plot of the varactor characteristic determine
the varactor capacitance at V
CC
/2. e.g. for a 2V V
CC
design the Siemens BB833 capacitance at 1V = 10pF
(approx.).
7. Using the following equation deduce the value of the
total stray parasitic capacitance C
P
.
C
P
=
@ #
~
2
p3
f
LO
2
3
L2
!
2
CV
where
C
V
= varactor capacitance at V
CC
/2
8. Using the following equation select the nearest value
for
L2
to centre the VCO at V
CC
/2.
1
~
2
p3
f
LO
2
!3~
C
P
1
C
V
!
9. By varying the PSU voltage confirm that the LO is
centred correctly at V
CC
/2, and that the oscillator
operates over the range 0V to V
CC
.
10. Disconnect the PSU and reconnect R1. Measure the
value at LF output using a
3
10 probe and an
oscilloscope. This should be a direct voltage with no
ripple at V
CC
/2 (
6
0.3V). If not repeat steps 1 to 8. To
compensate for non standard inductor values vary the
value of C18 and C11 to vary the capacitance of the
varactor to centre the V
CC
at V
CC
/2.
NOTE: It is important to minimise stray capacitance in
the VCO circuit to ensure that the VCO starts oscillat-
ing. The use of a varactor with a low capacitance at
zero bias is advisable. Similarly, reducing the values of
C11 and C18 whilst increasing L2 will help to reduce
the capacitance of the varactor at 0V, improving the re-
liability of the oscillator. A compact design methodology
is recommended for the VCO circuit components L2,
C11, C18 and D1.
L2
=
1
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