參數(shù)資料
型號: KESRX05
廠商: Zarlink Semiconductor Inc.
英文描述: 260 to 470MHz ASK Receiver with Power Down
中文描述: 260至470MHz ASK接收機(jī)的斷電
文件頁數(shù): 12/28頁
文件大?。?/td> 466K
代理商: KESRX05
11
KESRX05
VCO
19
16
VCO1
VCO2
L2
C11
C18
LF
4
64
23/24
XTAL1/2
XTAL1
R1
R4
D1
18
PHASE
DETECTOR
KESRX05
C12
C1
R2
CONNECTOR
CHARACTERISATION
R
TEST
(=R1)
PSU
+ -
Figure 3 Characterising the VCO/PLL operation
IF Amp/RSSI Detector
This is a log amplifierwith a small signal gain
.
80dB and
an RSSI output used as the detector. The 3dB bandwidth
of the IF log amplifier is typically 45MHz to allow for high
IFs to be used. However, normally, this wide IF bandwidth
would limit the overall sensitivity of the receiver due to the
amplified wideband noise generated in the first IF stage.
Since the RSSI detector is not frequency selective, any
wide band noise introduced after the intermediate filter CF1
will be detected as signal. A simple LC noise reduction
filter is therefore positioned part way down the log amplifier
to reduce the noise power from the earlier stages. Typically
this filter only needs to be a fixed component parallel LC
filter (L5 and C7) between pins IFFLT1 and IFFLT2 with a
1 MHz bandwidth (i.e. Q ~10). There are two internal 20k
damping resistors across these pins which will determine
the Q and the choice of L and C values (AC equivalent
circuit = 20k
), i.e:
An external damping resistor can be used to lower the Q
of the tuned LC circuit. This will alter the gain of the log
amplifier, i.e., slope and gradient of Figure 15. The objective
of the damping resistor is to prevent mis-tuning of the LC
circuit due to component tolerancing and thus degrading
the sensitivity of the receiver. The sensitivity results shown
in Figures 19 and 20 and in the AC Electrical Characterisics
(1) apply with no external damping resistor and the LC
circuit correctly tuned to 10·7MHz. The preferred alternative
to a damping resistor is to lower the Q of the the inductor
L5 or to increase the tolerance of C6.
A ceramic resonator or filter is not a recommended here
as the external LC filter provides a low impedance DC
path to remove any DC voltage offsets at the output of the
high gain log amplifier, RSSI pin 27. Further improvement
in sensitivity can be gained by increasing the Q of the
parallel LCfilter, provided that tolerancing of the LC filter is
taken into account.
For a low IF receiver,
,
1 MHz, a low pass filter can be
used for both the IF and noise reduction filter. Such a
receiver, however, will have virtually no image rejection
capability, and will thus have a 3dB penality in noise factor,
impairing the ultimate sensitivity of the receiver by a
minimum of 3dB.
The RSSI output transfer characteristic, at the RSSI pin,
has a slope of about 16mV/d B. A typical transfer
characteristic from RFIN input to RSSI output is plotted in
Figures 14 and 15, measured with a constant wave (n0
modulation RF input signal. This shows the effect of the
AGC in extending the range of the detector to
.1
10dBm
RF input signal and includes the effect of the AGC circuit
adapting to this signal level.
Because the RF amplifier AGC has a fast attack time and
slow decay time characteristic, the gain of the stage
remains constant during the data burst. This means that
the change in output for a given extinction ratio also remains
constant at approximately 16mV/dB up to peak input signal
levels
.1
10dBm. This requires the decay time constant
to exceed the transmitted bit period and no long period of
zero signal power has been transmitted.
Increasing the decay time constant of the AGC circuit by
increasing the value of C8 will impair the settling time (time
to good data) of the receiver. When duty cycling the
2
3
10
4
2
p
f
IF
Q
L
=
1
(2
p
f
IF
)
2
L
C
=
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