參數(shù)資料
型號： KD16902
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Virtual Surround Processor(虛擬環(huán)繞處理器)
中文描述： 虛擬環(huán)繞聲處理器（虛擬環(huán)繞處理器）
文件頁數(shù)： 9/74頁
文件大?。?/td> 327K
代理商： KD16902
HARDWARE DESCRIPTION
KD16902 VIRTUAL SURROUND PROCESSOR
9
Digital Audio Interface
Digital audio interface (SIPO/PISO) has three 3 serial inputs and 4 serial outputs for the 6 channel input and the 8
channel output. It supports 16/18/20/24 bit EIAJ (right-justified) and IIS (left-justified) format. The SIPO/PISO unit
interrupts DSP core after serial in/out completion. The left and right channels are distinguished by USR0 and USR1
flag as follows:
L-ch Input: INT1=1, USR0=0, R-ch Input: INT1=1, USR0=1
L-ch Output: INT2=1, USR1=0, R-ch Input: INT2=1, USR1=1
Table 4. Word / Bit Clock Control
Control
Description
Remark
IBCC
0
Synchronize with falling edge of BCKI
1
Synchronize with rising edge of BCKI
OBCC
0
Synchronize with falling edge of BCKO
1
Synchronize with rising edge of BCKO
LRCC
0
LRCKI(LRCKO)=L; L-ch data In/Out (default)
Controlled by HOST
1
LRCKI(LRCKO)=H; L-ch data In/Out
Table 5. Data Input Format
Control
Output Data Format
Remark
SDIF[2]
SDIF[1]
SDIF[0]
Right-
justify
(EIAJ)
0
0
0
MSB first 16 bit, 32/48/64 fs
Slave
Mode
0
0
1
MSB first 18 bit, 48/64 fs
0
1
0
MSB first 20 bit, 48/64 fs
0
1
1
MSB first 24 bit, 48/64 fs
Left-
justify
(IIS)
1
0
0
16 bit, 32/48/64 fs
1
0
1
18 bit, 48/64 fs
1
1
0
20 bit, 48/64 fs
1
1
1
24 bit, 48/64 fs
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