參數(shù)資料
型號： KD16902
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Virtual Surround Processor(虛擬環(huán)繞處理器)
中文描述： 虛擬環(huán)繞聲處理器（虛擬環(huán)繞處理器）
文件頁數(shù)： 5/74頁
文件大?。?/td> 327K
代理商： KD16902
PRODUCT OVERVIEW
KD16902 VIRTUAL SURROUND PROCESSOR
5
Pin Descriptions
Table 2. KD16902 Pin Descriptions (Type; pd=Pull-down, pu=Pull-up)
Pin Name
Number
I/O
Type
Pin Description
VDD
8,17,23,41,57
.
-
Power supply pins; 5.0 volt
GND
9,16,22,42,58
.
-
Ground pins
SFLRI
1
I
-
Serial digital audio signal input, Front Left/Right input
SRLRI
2
I
-
Serial digital audio signal input, Rear Left/Right input
SCSI
3
I
-
Serial digital audio signal input, Center/Subwoofer input
LRCKI
4
I
-
L/R word Clock Input of serial digital audio in
BCKI
5
I
-
Bit Clock Input of serial digital audio in
IBCC
6
I
pd
Input Bit Clock Control(0:normal, 1:reverse)
LRCKO
7
I
-
L/R word Clock Input of serial digital audio out
BCKO
10
I
-
Bit Clock Input of serial digital audio out
OBCC
11
I
pd
Output Bit Clock Control(0:normal, 1:reverse)
SFLRO
12
O
Serial digital audio signal output, Front Left/Right output
SRLRO
13
O
Serial digital audio signal output, Rear Left/Right output
SCSO
14
O
Serial digital audio signal output, Center/Subwoofer output
SVLRO
15
O
Serial digital audio signal output, Left/Right output to VCR
USR0~1
18~19
O
Test pin
XI
20
I
-
Crystal input when CKSEL=1; 16.934 MHz (dedicated)
XO
21
O
-
Crystal output
CKI
24
I
-
External Clock Input
CKSEL
25
I
pd
Select crystal/external; 1: crystal input, 0: external clock input
SHI
26
I
-
Serial Host Input
HWEN
27
I
-
Host Write Enable; Low active
HBCK
28
I
-
Host Bit Clock of serial data in
RESB
29
I
pu
Asynchronous Reset. Effective when CKI is rising
INT0~1
30~32
O
Test pin
EXT0~15
33~40,43~50
I/O
pu
Test pin; External bus data
TDO
51
O
Test pins; Test Output@TMS=1 / Nand-tree output@TMS=0
TMS
52
I
pd
Test pin; Test Mode Select (1: test mode, 0: normal mode)
TDI
53
I
pd
Test pins; Test Input@TMS=1 / Nand-tree input@TMS=0
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