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參數(shù)資料
| 型號： | KB2516 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 三路8位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 250K |
| 代理商： | KB2516 |
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
13
Figure 1 is a block diagram of the pre-amp that is used in AD2516X. A clamp circuit is required to set the input
DC level because the RGB signal input is AC coupled as it passes through the capacitor to be sent to the pre-
amp. The signal to control the clamp is made from the HSYNC signal in the sync processor block. The clamp
level control, which uses an 8-bit DAC, has two modes, first, the coarse level control that controls 3 RGB
channels simultaneously and, second, the fine level control that controls each channel clamp level independently.
The input signal is gain controlled through the 8-bit DAC for a maximum gain amplification of 2.3dB. As in the
clamp level control, the pre-amp has two modes: 1.) coarse level control that controls 3 RGB channels
simultaneously and 2.) fine level control which controls them independently.
T/H
15
Comps
Vref_tap
Gen.
D
O
OVF
UDF
Channel A<7:0>
8
Channel B<7:0>
8
8
4
5
T/H
VIN
31
Comps
Output Mode
Control
Figure 2. ADC Block Diagram
Figure 2 which has the 2-step pipeline configuration is a block diagram of the ADC used in AD2516X. It uses 1
overlap bit for digital correction and supports 3 output modes, signal channel mode, dual channel interleaving
mode, and dual channel parallel mode.
The sync processor block converts the HSYNC or SOG input to a positive HSYNC signal, which can be
processed by PLL, and also makes the clock signal needed for clamp level control from the HSYNC. When
HSYNC and SOG inputs enter simultaneously, it is designed to place priority on the HSYNC.
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