參數(shù)資料
型號: KB2511B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: ACB 14C 14#16 PIN RECP BOX
中文描述: 偏轉(zhuǎn)處理器多同步監(jiān)測儀
文件頁數(shù): 33/35頁
文件大小: 337K
代理商: KB2511B
KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
32
Figure 18. AGC Loop Block Diagram
I
2
C Control Adjustments
Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are
generated internally. Their amplitude are adjustable by their respective I
2
C register. They can also be inhibited by
their select bit. Endly, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude
control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this
stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I
2
C register
(vertical position). Its value is VPOS = 7/16
V
REF
±
300mV.
Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from
V
REF-V
, the bias voltage sent to the non-inverting input of booster should also derive from V
REF-V
to optimize the
accuracy(see Application Diagram).
Basic Equations
In first approximation, the amplitude of the ramp on pin 23 (Vout) is:
V
OUT
- VPOS = ( V
OSC
- V
DCMID
)
( 1 + 0.25 (V
AMP
) )
with:
- V
DCMID
= 7/16
V
REF
( typically 3.5V, the middle value of the ramp on pin 22)
- V
OSC
= V22 ( ramp with fixed amplitude)
- VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum
- VPOS is calculated by : VPOS = V
DCMID
+ 0.3Vp with Vp equals -1 for minimum vertical position register value
and +1 for maximum
The current available on Pin 22 is :
2
SYNCHRO
POLARITY
OSCILLATOR
20
-
+
22
Switch
Dlech
23
+
-
V-SYNC
DISCH.
OSC
CHARGE CURRENT
TRANSCONDUCTANCE
AMPLIFIER
REF
SAMP
CAP
SAMPLING
S CORRECTION
VS_AMP
SUB07/8bits
COR-C
SUB08/6bits
C CORRECTION
Vlow
18
VERT_AMP
SUB05/7BITS
VMOIRE
SUB0C/5BITS
VOSITION
SUB06/7BITS
VOUT
BREATH
I
OSC
= 3
V
REF
C
OSC
f
8
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