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參數資料
| 型號： | KAD5510P-12Q48 |
| 廠商： | Intersil |
| 文件頁數： | 7/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT CMOS 125MSPS 48QFN |
| 標準包裝： | 100 |
| 系列： | FemtoCharge™ |
| 位數： | 10 |
| 采樣率（每秒）： | 125M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 205mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
| 輸入數目和類型： | * |
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KAD5510P
15
FN7693.2
May 2, 2011
Theory of Operation
Functional Description
The KAD5510P is based upon a 10-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(Figure 22). The input voltage is captured by a Sample-Hold Amplifier
(SHA) and converted to a unit of charge. Proprietary charge-domain
techniques are used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each input
value. The converter pipeline requires six samples to produce a result.
Digital error correction is also applied, resulting in a total latency of
seven and one half clock cycles. This is evident to the user as a time lag
between the start of a conversion and the data being available on the
digital outputs.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
DNC pins must not be pulled up or down
SDO must be high
RESETN will be pulled low by the ADC during POR then
released
SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the previously mentioned conditions cannot be met at
power-up.
The SDO pin requires an external 4.7k
Ω pull-up to OVDD. If the
SDO pin is pulled low externally during power-up, calibration will
not be executed properly.
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high starting the calibration
sequence. When the RESETN pin is driven by external logic, it
should be connected to an open-drain output with open-state
leakage of less than 0.5mA to assure exit from the reset state. A
driver that can be switched from logic low to high impedance can
also be used to drive RESETN provided the high impedance state
leakage is less than 0.5mA and the logic voltages are the same.
The calibration sequence is initiated on the rising edge of RESETN, as
shown in Figure 23. The over-range output (OR) is set high once RESETN
is pulled low, and remains in that state until calibration is complete. The
OR output returns to normal operation at that time, so it is important
that the analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range condition, the OR
pin will stay high, and it will not be possible to detect the end of the
calibration cycle.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is deasserted.
At 250MSPS the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
FIGURE 22. ADC CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
LVDS/LVCMOS
OUTPUTS
+
–
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