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參數(shù)資料
| 型號(hào)： | KAD5510P-12Q48 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/31頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT CMOS 125MSPS 48QFN |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 205mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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KAD5510P
21
FN7693.2
May 2, 2011
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 16
for write operations and fSAMPLE divided by 66 for reads. At
fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and
3.79MHz for read operations. There is no minimum SCLK rate but
the ADC clock (CLKP/CLKN) must be active to access the SPI
registers.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described below). A dedicated serial data output pin (SDO) can
be activated by setting 0x00[7] high to allow operation in four-
wire mode.
SDO should always be connected to OVDD with a 4.7k resistor
even if not used. If the 4.7k resistor is not present the ADC will
not exit the reset state.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5510P functioning as a slave.
Multiple slave devices can interface to a single master in three-
wire mode only, since the SDO output of an unaddressed device
is asserted in four-wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high to low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 3). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 36,
and timing values are given in the “Switching Specifications” on
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
2-byte and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order can be
selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to
accommodate various microcontrollers.
Bit 7 SDO Active
FIGURE 39. N-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
LAST LEGAL
CSB STALLING
TABLE 3. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
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