參數(shù)資料
型號： KA2511B
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測儀
文件頁數(shù)： 32/35頁
文件大小： 337K
代理商： KA2511B
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B
31
EW
EWOUT = 2.5V + K1 ( V
OUT
- V
DCMID
)
2
+ K2 ( V
OUT
- V
DCMID
)
K1 is adjustable by EW amplitude I
2
C register
K2 is adjustable by keystone I
2
C register
Dynamic horizontal phase control
IOUT = K3 ( V
OUT
- V
DCMID
)
2
+ K4 ( V
OUT
- V
DCMID
)
K4 is adjustable by side pin balance I
2
C register
K3 is adjustable by parallelogram I
2
C register.
Function
When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an
external capacitor, C
OSC
= 150nF, the typical free running frequency is 100Hz.
Typical free running frequency can be calculated by:
A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can syn-
chronise the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor connected on
pin 22. A capacitor in the range [150nF, 220nF]
±
5% is recommanded for application in the following range: 50Hz
to 165Hz.
Typical maximum and minimum frequency, at 25
°
C and without any correction (S correction or C correction), can
be calculated by:
f
(Max.)
= 2.5 x f
0
and f
(Min.)
= 0.33 x f
0
If S or C corrections are applied, these values are slighty affected.
If a synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more con-
stant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp pin
22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance ampli-
fier generates the charge current of the capacitor. The ramp amplitude becomes again constant.
The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.
It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.
Good stability of the internal closed loop is reached by a 470nF
±
5% capacitor value on pin 20 (VAGC)
f
0
(Hz)= 1.5
10
-5
C
OSC
1
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