參數(shù)資料
型號(hào)： K7A403609A
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
中文描述： 128K × 36至
文件頁(yè)數(shù)： 2/17頁(yè)
文件大小： 466K
代理商： K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
- 2 -
Rev 3.0
August 2000
K7A403609A
128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
The K7A403609A and K7A401809A are 4,718,592-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system
′
s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609A and K7A401809A are fabricated using
SAMSUNG
′
s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V+0.3V/-0.165V Power Supply.
V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a linear
burst.
Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A .
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
128Kx36 , 256Kx18
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0~A
′
1
A0~A1
or A2~A17
A0~A16
or A0~A17
A2~A16
or DQa0 ~ DQb7
DQPa ~ DQPb
36 or 18
FAST ACCESS TIMES
PARAMETER
Symbol
-30
-27
-25
-22
-20
-18
Unit
Cycle Time
tCYC
3.3
3.6
4.0
4.4
5.0
5.4
ns
Clock Access Time
tCD
2.2
2.2
2.4
2.6
2.8
3.0
ns
Output Enable Access Time
tOE
2.2
2.2
2.4
2.6
2.8
3.0
ns
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