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參數(shù)資料
| 型號(hào)： | K7A403600B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36/x32 & 256Kx18 Synchronous SRAM |
| 中文描述： | 128Kx36/x32 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 470K |
| 代理商： | K7A403600B |
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
- 16 -
Rev 1.0
Nov 2001
K7A403200B
K7A403600B
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
Data
Address
CLK
ADS
64-Bits
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
128Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
128Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:17]
A
[17]
A
[0:16]
A
[17]
A
[0:16]
I/O
[0:71]
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
Clock
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
t
CSH
CD
t
LZC
Q2-1
Don
′
t Care
Undefined
*Notes :
n = 14 32K depth
15 64K depth
16 128K depth
17 256K depth
(ADSP CONTROLLED , ADSC=HIGH)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| K7A403600B_06 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A403600B-PC16000 | 制造商:Samsung SDI 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 3.5ns 100-Pin TQFP Tray |
| K7A403600B-QC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A403600M-QC14000 | 制造商:Samsung SDI 功能描述:DS |
| K7A403600M-QC16 | 制造商:Samsung Electro-Mechanics 功能描述:128K X 36 CACHE SRAM, 3.5 ns, PQFP100 |
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