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參數(shù)資料
| 型號(hào)： | K7A403600B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36/x32 & 256Kx18 Synchronous SRAM |
| 中文描述： | 128Kx36/x32 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 470K |
| 代理商： | K7A403600B |
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K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
- 10 -
Rev 1.0
Nov 2001
K7A403200B
K7A403600B
AC TIMING CHARACTERISTICS
(T
A
=0 to 70
°
C, V
DD
=3.3V+0.3V/-0.165V)
Notes :
1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP
is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times
whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
PARAMETER
Symbol
-16
-14
Unit
Min
Max
Min
Max
Cycle Time
tCYC
6.0
-
7.2
-
ns
Clock Access Time
tCD
-
3.5
-
4.0
ns
Output Enable to Data Valid
tOE
-
3.5
-
4.0
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
ns
Output Hold from Clock High
tOH
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
3.5
-
4.0
ns
Clock High to Output High-Z
tHZC
1.5
3.5
1.5
4.0
ns
Clock High Pulse Width
tCH
2.4
-
2.8
-
ns
Clock Low Pulse Width
tCL
2.4
-
2.8
-
ns
Address Setup to Clock High
tAS
1.5
-
1.5
-
ns
Address Status Setup to Clock High
tSS
1.5
-
1.5
-
ns
Data Setup to Clock High
tDS
1.5
-
1.5
-
ns
Write Setup to Clock High (GW, BW, WEX)
tWS
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
tADVS
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
tCSS
1.5
-
1.5
-
ns
Address Hold from Clock High
tAH
0.5
-
0.5
-
ns
Address Status Hold from Clock High
tSH
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
ns
Write Hold from Clock High (GW, BW, WEX)
tWH
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
cycle
Output Load(B)
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
5pF*
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Z0=50
* Capacitive Load consists of all components of
the test environment.
30pF*
RL=50
353
/
1538
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
/
1667
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
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