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參數(shù)資料
| 型號： | K7A401800M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx18 Synchronous SRAM |
| 中文描述： | 256Kx18同步SRAM |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 283K |
| 代理商： | K7A401800M |
K7A401800M
256Kx18 Synchronous SRAM
- 4 -
Rev 2.0
March 1999
FUNCTION DESCRIPTION
The K7A401800M is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power
PC based microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and dura-
tion of the burst access is controlled by ADSP, ADSC, ADV and Chip Select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip
address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In
read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of
CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to
the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The
address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled Low. And ADSP is
blocked to control signals by disabling CS
1
.
All byte write is done by GW (regardless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is High.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP Low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa or WEb) sampled low. The WEa controls DQa
0
~ DQa
7
and DQPa, WEb controls DQb
0
~ DQb
7
and
DQPb. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC
and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And when this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
LBO PIN
HIGH
Case 1
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
First Address
Fourth Address
BURST SEQUENCE TABLE
(Linear Burst)
Case 1
A
1
A
0
First Address
0
0
1
1
1
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN
LOW
Case 2
Case 3
Case 4
A
1
0
1
1
0
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
0
0
1
A
0
1
0
1
0
Fourth Address
0
1
0
相關(guān)PDF資料 |
PDF描述 |
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| K7A403609A | 128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM |
| K7A801800B | 256Kx36 & 512Kx18 Synchronous SRAM |
| K7A803600B | 256Kx36 & 512Kx18 Synchronous SRAM |
| K7A801800M | 256Kx36 & 512Kx18 Synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7A401800M-QC14 | 制造商:Samsung Semiconductor 功能描述: |
| K7A401809A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM |
| K7A401809B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A401809B-QC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A403200B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
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