參數(shù)資料
型號: K5A3280YBC-T755
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: MCP MEMORY
中文描述: MCP的記憶
文件頁數(shù): 44/45頁
文件大小: 625K
代理商: K5A3280YBC-T755
MCP MEMORY
K5A3x80YT(B)C
Revision 0.0
November 2002
- 44 -
Preliminary
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS1
S
and low WE. A write begins when CS1
S
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1
S
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS1
S
going low to the end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
applied in case a write ends as CS1
S
or WE going high.
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
SRAM DATA RETENTION WAVE FORM
CS1
S
controlled
Vcc
S
2.7V
2.2V
V
DR
CS1
S
Vss
Data Retention Mode
CS1
S
Vcc
S
- 0.2V
t
SDR
t
RDR
t
AS(3)
CS1
S
CS2
S
CS2
S
controlled
Vcc
S
2.7V
CS2
S
0.4V
Vss
V
DR
Data Retention Mode
t
SDR
t
RDR
CS2
S
0.2V
t
CW(2)
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