參數(shù)資料
型號(hào)： K4T1G164QM-ZCCC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1Gb M-die DDR2 SDRAM Specification
中文描述： 1Gb的的M -模DDR2 SDRAM的規(guī)格
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 612K
代理商： K4T1G164QM-ZCCC
Page 27 of 28
Rev. 1.1 Aug. 2005
DDR2 SDRAM
1G A-die DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V
IH(ac)
level for a rising signal and V
IL(ac)
for a falling signal applied to the
device under test.
32. Input waverorm timing is referenced from the input signal crossing at the V
IL(dc)
) level for a rising signal and V
IH
(dc) for a falling signal applied to the
device under test.
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be mono-
tonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.
tIS
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
V
SS
CK
CK
tIH
tIS
tIH
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