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參數(shù)資料
| 型號(hào)： | K4T1G084QM-ZCCC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb M-die DDR2 SDRAM Specification |
| 中文描述： | 1Gb的的M -模DDR2 SDRAM的規(guī)格 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 612K |
| 代理商： | K4T1G084QM-ZCCC |
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Page 22 of 28
Rev. 1.1 Aug. 2005
DDR2 SDRAM
1G A-die DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied exter-
nally to VSS through a 20 ohm
to 10 K ohm
resisor to insure proper operation.
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
t
DS
t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS
DQS
D
DMin
DQS/
DQS
DQ
DM
t
DH
<Data input (write) timing>
DMin
DMin
DMin
D
D
D
V
IL
(ac)
V
IH
(ac)
V
IL
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
V
IL
(dc)
V
IH
(dc)
t
CH
t
CL
CK
CK
CK/CK
DQS/DQS
DQ
DQS
DQS
t
RPST
Q
t
RPRE
t
DQSQmax
t
QH
t
QH
t
DQSQmax
<Data output (read) timing>
Q
Q
Q
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