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參數(shù)資料
| 型號(hào)： | K4S281632B-TC1L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 128Mbit SDRAM的200萬× 16 × 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 108K |
| 代理商： | K4S281632B-TC1L |
K4S281632B
Rev. 0.0 Aug. 1999
CMOS SDRAM
The K4S281632B is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG
′
s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 16Bit x 4 Banks Synchronous DRAM
Bank Select
Data Input Register
2M x 16
2M x 16
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 16
2M x 16
Timing Register
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Part No.
Max Freq.
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
66MHz(CL=2 &3)
Interface Package
K4S281632B-TC/L75
K4S281632B-TC/L80
K4S281632B-TC/L1H
K4S281632B-TC/L1L
K4S281632B-TC/L10
LVTTL
54
TSOP(II)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4S281632B-TC10 | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TC1H | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TC75 | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TC80 | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TL10 | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S281632B-TC75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TC80 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TL10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TL1H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S281632B-TL1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
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