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參數(shù)資料
| 型號(hào)： | K4S280432M-TC80 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | K4S280432M-TC80 |
K4S280432M
CMOS SDRAM
Rev. 0.0 Aug. 1999
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70
°C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-80
-1H
-1L
-10
Operating current
(One bank active)
ICC1
Burst length = 1
tRC
≥ tRC(min)
IOL = 0 mA
120
110
105
mA
1
Precharge standby current in
power-down mode
ICC2P
CKE
≤ VIL(max), tCC = 15ns
1
mA
ICC2PS
CKE & CLK
≤ VIL(max), tCC = ∞
1
Precharge standby current
in non power-down mode
ICC2N
CKE
≥ VIH(min),CS ≥ VIH(min),tCC=15ns
Input signals are changed one time during 30ns
15
mA
ICC2NS
CKE
≥ VIH(min), CLK
≤ VIL(max), tCC = ∞
Input signals are stable
7
Active standby current
in power-down mode
ICC3P
CKE
≤ VIL(max), tCC = 15ns
5
mA
ICC3PS
CKE & CLK
≤ VIL(max), tCC = ∞
5
Active standby current
in non power-down mode
(One bank active)
ICC3N
CKE
≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns.
30
mA
ICC3NS
CKE
≥ VIH(min), CLK
≤ VIL(max), tCC = ∞
Input signals are stable
20
mA
Operating current
(Burst mode)
ICC4
IOL = 0 mA
Page burst
tCCD = 2CLKs
3
140
115
mA
1
2
105
115
105
Refresh current
ICC5
tRC
≥ tRC(min)
200
165
mA
2
Self refresh current
ICC6
CKE
≤ 0.2V
C
1.5
mA
3
L
800
uA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S280432M-C**
4. K4S280432M-L**
Notes :
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| K4S280832A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
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| K4S280832A-TC/L1H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S280832A-TC/L1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
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