參數(shù)資料
型號： K4H561638M-TLB0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
元件分類： ADC
英文描述： 10-Bit, 164 kSPS ADC Parallel Out, Direct I/F to DSP/uProcessor, 10 Ch. 24-SOIC -40 to 85
中文描述： 128MB DDR SDRAM的
文件頁數(shù)： 14/18頁
文件大?。?/td> 168K
代理商： K4H561638M-TLB0
DDR SDRAM
DDR SDRAM 256Mb D-die (x8, x16)
AC Timing Parameters and Specifications
Rev. 1.1 Feb. 2003
Parameter
Symbol
- CC(DDR400@CL=3)
Min
55
70
40
15
15
10
15
2
5
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
- C4(DDR400@CL=3)
Min
60
70
40
18
18
10
15
2
5
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
Unit
Note
Max
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Internal write to read command delay
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ps
tCK
tCK
tCK
tCK
70K
70K
Clock cycle time
CL=3.0
CL=2.5
tCK
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
16
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
Write preamble setup time
Write preamble
Write postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDSS
tDSH
tDQSH
13
5
0.6
0.6
4
tCK
DQS-in low level width
Address and Control Input setup time
Address and Control Input hold time
tDQSL
tIS
tIH
0.35
0.6
0.35
0.6
tCK
ns
h,7~10
h,7~10
0.6
0.6
ns
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
Control & Address input pulse width for each input
tHZ
tLZ
tMRD
tDS
tDH
tDIPW
tIPW
-
tAC max
tAC max
-
tAC max
tAC max
ns
ns
tCK
ns
ns
ns
ns
us
us
3
3
tAC min
2
0.4
0.4
1.75
2.2
15.6
7.8
tHP
-tQHS
min
tCH/tCL
tAC min
2
0.4
0.4
1.75
2.2
15.6
7.8
tHP
-tQHS
min
tCH/tCL
i, j
i, j
9
9
Refresh interval time
Up to 128Mb
tREFI
6
256Mb, 512Mb, 1Gb
Output DQS valid window
tQH
-
-
ns
12
Clock half period
tHP
-
-
ns
11, 12
相關(guān)PDF資料
PDF描述
K4H561638F-UCC4 256Mb F-die DDR400 SDRAM Specification
K4H561638F-UCCC 256Mb F-die DDR400 SDRAM Specification
K4H561638A-TCA2 128Mb DDR SDRAM
K4H561638A-TCB0 128Mb DDR SDRAM
K4H561638A-TLA0 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-PLCC
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