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參數(shù)資料
| 型號： | K4H561638F-UCCC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mb F-die DDR400 SDRAM Specification |
| 中文描述： | 256Mb的的F -模具支持DDR400內(nèi)存規(guī)格 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | K4H561638F-UCCC |
DDR SDRAM
DDR SDRAM 256Mb D-die (x8, x16)
Rev. 1.1 Feb. 2003
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC ~ AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
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