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參數(shù)資料
| 型號： | K4H561638E-TCA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Enhanced Product 10-Bit Analog-To-Digital Converters W/Serial Control & 11 Analog Inputs 20-SOIC -40 to 125 |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 168K |
| 代理商： | K4H561638E-TCA2 |
DDR SDRAM
DDR SDRAM 256Mb D-die (x8, x16)
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.
Rev. 1.1 Feb. 2003
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Table 5 : Output Slew Rate Characteristice (X8 Devices only)
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Table 7 : Output Slew Rate Matching Ratio Characteristics
Delta Slew Rate
tDS
tDH
UNITS
NOTES
+/- 0.0 V/ns
0
0
ps
i
+/- 0.25 V/ns
+50
+50
ps
i
+/- 0.5 V/ns
+100
+100
ps
i
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
NOTES
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
NOTES
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g
AC CHARACTERISTICS
DDR400
PARAMETER
MIN
MAX
NOTES
Output Slew Rate Matching Ration (Pullup to Pulldown)
-
-
e,k
Table 1 :
Input Slew Rate for DQ, DQS, and DM
Table 2
:
Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
AC CHARACTERISTICS
DDR400
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
0.5
4.0
V/ns
a, k
Input Slew Rate
tIS
tIH
UNITS
NOTES
0.5 V/ns
0
0
ps
h
0.4 V/ns
+50
0
ps
h
0.3 V/ns
+100
0
ps
h
Input Slew Rate
tDS
tDH
UNITS
NOTES
0.5 V/ns
0
0
ps
j
0.4 V/ns
+75
+75
ps
j
0.3 V/ns
+150
+150
ps
j
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H561638E-TCB0 | Enhanced Product 10-Bit Analog-To-Digital Converters W/Serial Control & 11 Analog Inputs 20-SOIC -40 to 125 |
| K4H561638E-TLA0 | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, Single Ch. 8-SOIC |
| K4H561638E-TLA2 | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, Single Ch. 8-SOIC |
| K4H561638E-TLB0 | 128Mb DDR SDRAM |
| K4H561638F-TCC4 | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, Single Ch. 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H561638E-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H561638E-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H561638E-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H561638E-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H561638F | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb F-die DDR SDRAM Specification |
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