參數(shù)資料
型號： K4H560438E-NC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DIODE ZENER SINGLE 300mW 43Vz 5mA-Izt 0.02 0.05uA-Ir 33 SOT-23 3K/REEL
中文描述： 256Mb的電子芯片DDR SDRAM內(nèi)存規(guī)格54pin sTSOP（二）
文件頁數(shù)： 18/26頁
文件大?。?/td> 291K
代理商： K4H560438E-NC
- 18 -
K4H560838D
DDR SDRAM
Rev. 2.2 Mar. ’03
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t
RCD
satisfied after this command.
5. For registered DIMMs, t
CL
and t
CH
are
≥
45% of the period including both the half period jitter (t
JIT(HP)
) of the PLL and the half period
jitter due to crosstalk (t
JIT
(crosstalk)
) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
tIS
tIH
(V/ns)
(ps)
(ps)
This derating table is used to increase t
IS
/t
IH
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
This derating table is used to increase t
DS
/t
DH
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Parameter
Symbol
B3
(DDR333)
Min
A2
(DDR266A)
Min
B0
(DDR266B)
Min
Unit
Note
Max
Max
Max
Mode register set cycle time
tMRD
12
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
ns
7,8,9
Control & Address input pulse width
tIPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
Power down exit time
tPDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
ns
4
Exit self refresh to read command
tXSRD
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
5
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
Data hold skew factor
tQHS
0.5
0.75
0.75
ns
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
3
Active to Read with Auto precharge
command
tRAP
18
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
11
Input Setup/Hold Slew Rate
0.5
0
0
0.4
0.3
+50
+100
+50
+100
I/O Setup/Hold Slew Rate
(V/ns)
tDS
(ps)
tDH
(ps)
0.5
0.4
0
0
+75
+75
0.3
+150
+150
相關(guān)PDF資料
PDF描述
K4H560438M-TCA0 DIODE ZENER DUAL COMMON-CATHODE 300mW 51Vz 5mA-Izt 0.0588 0.1uA-Ir 38 SOT-23 3K/REEL
K4H560438E-ULA2 256Mb E-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)
K4H560438E-ULAA 256Mb E-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)
K4H560438E-ULB0 256Mb E-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)
K4H560438E-VLB0 256Mb E-die DDR SDRAM Specification 54 sTSOP-II with Pb-Free (RoHS compliant)
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參數(shù)描述
K4H560438E-NC/LA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
K4H560438E-NC/LB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
K4H560438E-NC/LB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
K4H560438E-NCA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
K4H560438E-NCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II)
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