參數(shù)資料
型號(hào)： K4H510438M-TLA2
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Dual Wide Bandwidth High Output Drive Single Supply Op Amp 8-PDIP 0 to 70
中文描述： 128MB DDR SDRAM的
文件頁數(shù)： 12/24頁
文件大?。?/td> 367K
代理商： K4H510438M-TLA2
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
IDD7A : Operating current: Four bank operation
1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C
Worst Case : Vdd = 2.7V, T= 10’ C
2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
IDD1 : Operating current: One bank operation
1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C
Worst Case : Vdd = 2.7V, T= 10’c
2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
3. Timing patterns
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A
相關(guān)PDF資料
PDF描述
K4H510438M-TLB0 Dual Wide Bandwidth High Output Drive Single Supply Op Amp 8-PDIP 0 to 70
K4H511638C-TCA0 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-SOIC
K4H511638C-TCA2 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-SOIC
K4H511638C-TCB0 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-SOIC
K4H511638C-TLA0 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-PDIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4H510438M-TLB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H510638E-TC/LA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)
K4H510638E-TC/LAA 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)
K4H510638E-TC/LB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)
K4H510738E 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)
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