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參數資料
| 型號： | K4D553238F-JC36 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | ; Accuracy: 1%; Current Rating:5A; Current Ratio:100:5 A; Terminal Type:Leaded RoHS Compliant: Yes |
| 中文描述： | 片256Mbit GDDR SDRAM內存 |
| 文件頁數： | 14/17頁 |
| 文件大?。?/td> | 297K |
| 代理商： | K4D553238F-JC36 |
256M GDDR SDRAM
K4D553238F-JC
- 14 -
Rev 1.0 (Mar. 2004)
Note 1 :
- The JEDEC GDDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
1
tHP
CK, CK
DQS
DQ
CS
2
5
0
COMMAND
READA
tQH
Qa0
tDQSQ(max)
tDQSQ(max)
Qa1
3
4
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