參數(shù)資料
型號(hào)： K4D551638F-TC50
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit GDDR SDRAM
中文描述： 片256Mbit GDDR SDRAM內(nèi)存
文件頁數(shù)： 13/16頁
文件大?。?/td> 206K
代理商： K4D551638F-TC50
256M GDDR SDRAM
K4D551638F-TC
- 13 -
Rev 1.7 (June 2004)
Target Spec
AC CHARACTERISTICS
Parameter
Symbol
-33
-36
-40
-50
-60
Unit
Note
Min
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Max
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
Min
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
Min
4.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
Min
5.0
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.35
0.35
0.6
0.6
0.4
0.4
tCLmin
or
tCHmin
Max
10
0.55
0.55
0.55
0.65
0.4
1.1
0.6
1.28
-
-
0.6
-
-
-
-
-
-
Min
6.0
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.4
0.35
0.35
0.8
0.8
0.45
0.45
tCLmin
or
tCHmin
tHP-
0.55
Max
12
0.55
0.55
0.6
0.7
0.45
1.1
0.6
1.25
-
-
0.6
-
-
-
-
-
-
CK cycle time
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup tIS
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
CL=3
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
1
tIH
tDS
tDH
Clock half period
tHP
-
-
-
-
-
ns
1
Data output hold time from DQS
tQH
-
tHP-0.4
-
tHP-0.4
-
tHP-0.5
-
-
ns
1
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming
the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
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