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參數(shù)資料
| 型號： | K4D551638F-TC40 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR SDRAM |
| 中文描述： | 片256Mbit GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 206K |
| 代理商： | K4D551638F-TC40 |
256M GDDR SDRAM
K4D551638F-TC
- 11 -
Rev 1.7 (June 2004)
Target Spec
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, T
A
=0 to 65
°
C)
Note :
1. Measured with outputs open.
2. Refresh period is 64ms
Parameter
Symbol
Test Condition
Version
Unit
Note
-33
-36
-40
-50
-60
Operating Current
(One Bank Active)
I
CC1
Burst Lenth=2
t
RC
≥
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
TBD
TBD
TBD
150
125
mA
1
Precharge Standby Current
in Power-down mode
I
CC2
P
CKE
≤
V
IL
(max),
t
CC
=
t
CC
(min)
TBD
TBD
TBD
4
3
mA
Precharge Standby Current
in Non Power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min),
t
CC
=
t
CC
(min)
TBD
TBD
TBD
25
20
mA
Active Standby Current
power-down mode
I
CC3
P
CKE
≤
V
IL
(max),
t
CC
=
t
CC
(min)
TBD
TBD
TBD
55
35
mA
Active Standby Current in
in Non Power-down mode
I
CC3
N
CKE
≥
VIH(min), CS
≥
VIH(min),
t
CC
=
t
CC
(min)
TBD
TBD
TBD
75
56
mA
Operating Current
(Burst Mode)
I
CC4
t
RC
≥
t
RFC
(min)
t
RC
≥
t
RFC
(min)
Page Burst, All Banks activated.
TBD
TBD
TBD
250
200
mA
Refresh Current
I
CC5
t
RC
≥
t
RFC
(min)
TBD
TBD
TBD
200
180
mA
2
Self Refresh Current
I
CC6
CKE
≤
0.2V
TBD
TBD
TBD
3
3
mA
Operating Current
(4Bank Interleaving)
I
CC7
Burst Length=4
, t
RC
≥
t
RFC
(min)
I
OL
=0mA, t
CC
=
t
CC
(min)
TBD
TBD
TBD
380
350
mA
1. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same
Note :
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
=0V, V
DD
=2.6V+
0.1V, V
DDQ
=2.6V+
0.1V ,T
A
=0 to 65
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
V
IH
V
REF
+0.35
-
-
V
Input Low (Logic 0) Voltage; DQ
V
IL
-
-
V
REF
-0.35
V
Clock Input Differential Voltage; CK and CK
V
ID
0.7
-
V
DDQ
+0.6
V
1
Clock Input Crossing Point Voltage; CK and CK
V
IX
0.5*V
DDQ
-0.2
-
0.5*V
DDQ
+0.2
V
2
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