參數(shù)資料
型號： JZ48F4L0QBY
廠商： Intel Corp.
英文描述： StrataFlash Wireless Memory
中文描述： 無線的StrataFlash存儲器
文件頁數(shù)： 52/106頁
文件大?。?/td> 1272K
代理商： JZ48F4L0QBY
Intel StrataFlash Wireless Memory (L18)
April 2005
52
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation
for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is
cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data
word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value.
Figure 24
shows the data output latency for the different settings of LC[2:0].
Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however,
a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and
Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word
boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition
will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT
states.
Refer to
Table 11
and
Table 12
for Latency Code Settings.
15
Read Mode (RM)
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
14
Reserved (R)
Reserved bits should be cleared (0)
13:11
Latency Count (LC[2:0])
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
10
Wait Polarity (WP)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
9
Data Hold (DH)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8
Wait Delay (WD)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
7
Burst Sequence (BS)
0 =Reserved
1 =Linear (default)
6
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
5:4
Reserved (R)
Reserved bits should be cleared (0)
3
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0
Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Note:
Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1)
Wait must be deasserted with valid data (WD =
0). WD = 1 is not supported.
Table 10.
Read Configuration Register Description (Sheet 2 of 2)
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