參數(shù)資料
型號(hào)： JZ48F4L0QBY
廠商： Intel Corp.
英文描述： StrataFlash Wireless Memory
中文描述： 無(wú)線的StrataFlash存儲(chǔ)器
文件頁(yè)數(shù)： 42/106頁(yè)
文件大?。?/td> 1272K
代理商： JZ48F4L0QBY
Intel StrataFlash Wireless Memory (L18)
April 2005
42
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then V
CC
should attain V
CCMIN
before
applying V
CCQ
and V
PP
. Device inputs should not be driven before supply voltage equals V
CCMIN
.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Reset
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active-low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
System designers should guard against spurious writes when V
CC
voltages are above V
LKO
.
Because both WE# and CE# must be asserted for a write operation, deasserting either signal
inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because alteration
of memory contents can only occur after successful completion of a two-step command sequence
(see
Section 9.2, “Device Commands” on page 47
).
Nbr.
P1
Symbol
t
PLPH
Parameter
Min
100
-
-
60
Max
-
25
25
-
Unit
ns
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
CC
Power valid to RST# deassertion (high)
P2
t
PLRH
μs
P3
t
VCCPH
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
PLPH
is < t
PLPH
min, but this is not guaranteed.
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
If RST# is tied to the V
CC
supply, device will not be ready until t
VCCPH
after V
CC
≥
V
CC
min.
If RST# is tied to any supply/signal with V
CCQ
voltage levels, the RST# input voltage must not exceed
V
CC
until V
CC
≥
V
CC
(min).
Reset completes within t
PLPH
if RST# is asserted while no erase or program operation is executing.
7.
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